The present invention relates to a semiconductor memory circuit and, more particularly, to a dynamic semiconductor memory circuit which employs rows and columns provided with so-called one transistor storage cells.
In recent years, the one-transistor storage cell type memory device has been widely utilized as a random access memory (RAM) device of the MIS integrated semiconductor memory circuit. Such RAM device has already been disclosed in U.S. Pat. No. 4,045,783 or U.S. Pat. No. 4,195,357, and produces many superior advantages, as compared with a conventional RAM, however, at the same time, such RAM has some defects. The present invention addresses two of the defects. One defect resides in that read data from the RAM often contains an error due to a change in the level of the voltage of power source. The other defect resides in that error in the RAM system often occurs due to a change in the level of the back gate voltage (V.sub.BB) for biassing the substrate, in which the change of V.sub.BB is necessarily created in accordance with voltage change developed in the bit (column) line.